FERP Interface and Interconnect Cores for Stream Processing Applications

As SoC technology use increases, the question arises of how to connect the on-chip components. Current solutions use familiar components (such as busses and direct links) but these have throughput concerns and unnecessarily complicate the system design. This paper introduces the full/empty register pipe (FERP) interface and a collection of IP cores to support it. Along with its dataflow computational model, this interface is extremely well-suited for stream processing — an emerging computational model that is gaining popularity from embedded systems to supercomputers. An example is presented that illustrates how existing IP cores can be easily incorporated and how the resulting IP cores can be combined to perform complex, general stream-based algorithms.